In an error data correcting system of this type, which has been proposed heretofore in this field, n data words Wl to Wn each containing m bits additionally include a first check code ##EQU1## as the sum of bits corresponding to the data words and a second check code ##EQU2## as the sum of the bits corresponding to the signals generated through the operation of a polynomial X.sup.m +X.sup.g +1 by an auxiliary matrix (T). The error data correcting system can correct the error words up to two words by using an M matrix generator for decoding.
A ROM (read only memory) has generally been used for the M matrix generator for decoding, because of the time restriction in the decoding process.
In the case of an audio PCM recorder known as a record/reproduction system, for example, one word includes 12 to 16 bits, generally. If the error data correcting system is applied to such a system, the memory capacity of the ROM used must be considerably large and an address counter to control the ROM is further needed. The overall system accordingly is complicated in the circuit construction. Additionally, the number of components necessary when the circuit is fabricated by LSI technology, is enormous.